NEW M.2 PCIE NVME SSD 256GB 512GB 1T 2T HG2283+HYNIX V7

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NEW M.2 PCIE NVME SSD 256GB 512GB 1T 2T HG2283+HYNIX V7

M.2 2280 S2 NVME SSD HG2283+ Hynix V7 1.PRODUCT SPECIFICATIONS Capacity − 128GB, 256GB, 512GB, 1024GB, 2048GB − Support 32-bit addressing mode Electrical/Physical Interface − PCIe Interface − Compliant with NVMe 1.3 − PCIe Express Base Ver 3.1 − PCIe Gen 3 x 4 lane & backward compatible to...

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M.2 2280 S2 NVME SSD HG2283+ Hynix V7

1.PRODUCT SPECIFICATIONS

Capacity

− 128GB, 256GB, 512GB, 1024GB, 2048GB

− Support 32-bit addressing mode

Electrical/Physical Interface

− PCIe Interface

− Compliant with NVMe 1.3

− PCIe Express Base Ver 3.1

− PCIe Gen 3 x 4 lane & backward compatible to PCIe Gen 2 and Gen 1

− Support up to QD 128 with queue depth of up to 64K

− Support power management

Supported NAND Flash

− Support up to 16 Flash Chip Enables (CE) within a single design

− Support up to 4pcs of BGA132 flash

− Support 8-bit I/O NAND Flash

− Support Toggle2.0, Toggle3.0, ONFI 2.3, ONFI 3.0, ONFI 3.2 and ONFI 4.0 interface

Samsung V6 3D NAND

Hynix V7 3D NAND

ECC Scheme

− HG2283 PCIe SSD applies LDPC of ECC algorithm.

Sector Size Support

− 512B

− 4KB

UART/ GPIO

Support SMART and TRIM commands

LBA Range

− IDEMA standard

Performance

Performance of HG2283+Hynix V7 (1200Mbps)

Capacity	Flash Structure (BGA Package)	CE#	Flash Type	Sequential (CDM)		IOMeter
Capacity	Flash Structure (BGA Package)	CE#	Flash Type	Read (MB/s)	Write (MB/s)	Read (IOPS)	Write (IOPS)
128GB	DDP x 1	2	BGA132, Hynix V7	1650	1100	195K	260K
256GB	DDP x 2	4	BGA132, Hynix V7	3100	1850	360K	450K
512GB	QDP x 2	8	BGA132, Hynix V7	3100	2090	360K	475K
1024GB	QDP x 4	16	BGA132, Hynix V7	3100	2200	360K	480K
2048GB	ODP x 4	16	BGA132, Hynix V7	3100	2200	360K	480K

NOTES:

1. Performance was based on Hynix V7 TLC NAND flash.

POWER CONSUMPTION

Capacity	Flash Configuration (BGA Package)		Power Consumption³
Capacity	Flash Configuration (BGA Package)	Read (mW)	Write (mW)	PS3 (mW)	PS4 (mW)
128GB	DDP x 1	2940	2530	50	5
256GB	DDP x 2	4120	3400	50	5
512GB	QDP x 2	4090	3390	50	5
1024GB	QDP x 4	4050	3380	50	5
2048GB	ODP x 4	4440	3810	50	5

NOTES:

1. Data measured based on Hynix V7 512Gb mono die TLC Flash.

2. Power consumption is measured during the sequential read and write operations performed by IOMeter.

Flash Management

1.4.1. Error Correction Code (ECC)

Flash memory cells will deteriorate with use, which might generate random bit errors in the stored data. Thus, HG2283 PCIe SSD applies the LDPC (Low Density Parity Check) of ECC algorithm, which can detect and correct errors occur during read process, ensure data been read correctly, as well as protect data from corruption.

1.4.2. Wear Leveling

NAND flash devices can only undergo a limited number of program/erase cycles, when flash media is not used evenly, some blocks get updated more frequently than others and the lifetime of device would be reduced significantly. Thus, wear leveling is applied to extend the lifespan of NAND flash by evenly distributing write and erase cycles across the media.

HosinGlobal provides advanced wear leveling algorithm, which can efficiently spread out the flash usage through the whole flash media area. Moreover, by implementing both dynamic and static wear leveling algorithms, the life expectancy of the NAND flash is greatly improved.

1.4.3. Bad Block Management

Bad blocks are blocks that do not function properly or contain more invalid bits causing stored data unstable, and their reliability is not guaranteed. Blocks that are identified and marked as bad by the manufacturer are referred to as “Early Bad Blocks”. Bad blocks that are developed during the lifespan of the flash are named “Later Bad Blocks”. HosinGlobal implements an efficient bad block management algorithm to detect the factory-produced bad blocks and manages bad blocks that appear with use. This practice prevents data being stored into bad blocks and further improves the data reliability.

1.4.4. TRIM

TRIM is a feature which helps improve the read/write performance and speed of solid state drives (SSD). Unlike hard disk drives (HDD), SSDs are not able to overwrite existing data, so the available space gradually becomes smaller with each use. With the TRIM command, the operating system can inform the SSD so that blocks of data that are no longer in use can be removed permanently. Thus, the SSD will perform the erase action, which prevents unused data from occupying blocks at all time.

1.4.5. SMART

SMART, an acronym for Self-Monitoring, Analysis and Reporting Technology, is an open standard that allows a solid state drive to automatically detect its health and report potential failures. When a failure is recorded by SMART, users can choose to replace the drive to prevent unexpected outage or data loss. Moreover, SMART can inform users impending failures while there is still time to perform proactive actions, such as save data to another device.

1.4.6. Over-Provision

Over Provisioning refers to the preserving additional area beyond user capacity in a SSD, which is not visible to users and cannot be used by them. However, it allows a SSD controller to utilize additional space for better performance and WAF. With Over Provisioning, the performance and IOPS (Input/Output Operations per Second) are improved by providing the controller additional space to manage P/E cycles, which enhances the reliability and endurance as well. Moreover, the write amplification of the SSD becomes lower when the

controller writes data to the flash.

1.4.7. Firmware Upgrade

Firmware can be considered as a set of instructions on how the device communicates with the host. Firmware will be upgradable when new features are added, compatibility issues are fixed, or read/write performance gets improved.

1.4.8. Thermal Throttling

The purpose of thermal throttling is to prevent any components in a SSD from over-heating during read and write operations. HG2283 is designed with an on-die thermal sensor and with its accuracy; firmware can apply different levels of throttling to achieve the purpose of protection efficiently and proactively via SMART reading.

1.5. Advanced Device Security Features

1.5.1. Secure Erase

Secure Erase is a standard NVMe format command and will write all “0x00” to fully wipe all the data on hard drives and SSDs. When this command is issued, SSD controller will erase its storage blocks and return to its factory default settings.

1.5.2. Crypto Erase

Crypto Erase is a feature that erases all data of an OPAL-activated SSD or a “SED” (Security-Enabled Disk) drive by resetting the cryptographic key of the disk. Since the key is modified, the previously encrypted data will become useless, achieving the purpose of data security.

1.5.3. Physical Presence SID (PSID)

Physical Presence SID (PSID) is defined by TCG OPAL as a 32-character string and the purpose is to revert SSD back to its manufacturing setting when the drive is still OPAL-activated. PSID code can be printed on a SSD label when an OPAL-activated SSD supports PSID revert feature.

1.6. SSD Lifetime Management

1.6.1. Terabytes Written (TBW)

TBW (Terabytes Written) is a measurement of SSDs’ expected lifespan, which represents the amount of data

written to the device. To calculate the TBW of a SSD, the following equation is applied:

TBW = [(NAND Endurance) x (SSD Capacity)] / [WAF]

NAND Endurance: NAND endurance refers to the P/E (Program/Erase) cycle of a NAND flash.

SSD Capacity: The SSD capacity is the specific capacity in total of a SSD.

WAF: Write Amplification Factor (WAF) is a numerical value representing the ratio between the amount of data that a SSD controller needs to write and the amount of data that the host’s flash controller writes. A better WAF, which is near 1, guarantees better endurance and lower frequency of data written to flash memory.

TBW in this document is based on JEDEC 218/219 workload.

1.6.2. Media Wear Indicator

Actual life indicator reported by SMART Attribute byte index [5], Percentage Used, recommends User to replace drive when reaching to 100%.

1.6.3. Read Only Mode (End of Life)

When drive is aged by cumulated program/erase cycles, media worn-out may cause increasing numbers of later bad block. When the number of usable good blocks falls outside a defined usable range, the drive will notify Host through AER event and Critical Warning to enter Read Only Mode to prevent further data corruption. User should start to replace the drive with another one immediately.

1.7. Adaptive Approach to Performance Tuning

1.7.1. Throughput

Based on the available space of the disk, HG2283 will regulate the read/write speed and manage the performance of throughput. When there still remains a lot of space, the firmware will continuously perform read/write action. There is still no need to implement garbage collection to allocate and release memory, which will accelerate the read/write processing to improve the performance. Contrarily, when the space is going to be used up, HG2283 will slow down the read/write processing, and implement garbage collection to release memory. Hence, read/write performance will become slower.

1.7.2. Predict & Fetch

Normally, when the Host tries to read data from the PCIe SSD, the PCIe SSD will only perform one read action after receiving one command. However, HG2283 applies Predict & Fetch to improve the read speed. When the host issues sequential read commands to the PCIe SSD, the PCIe SSD will automatically expect that the following will also be read commands. Thus, before receiving the next command, flash has already prepared the data. Accordingly, this accelerates the data processing time, and the host does not need to wait so long to receive data.

1.7.3. SLC Caching

HG2283’s firmware design currently adopts dynamic caching to deliver better performance for better endurance and consumer user experience.

3. ENVIRONMENTAL SPECIFICATIONS

3.1. Environmental Conditions 3.1.1. Temperature and Humidity

Table 3-1 High Temperature

	Temperature	Humidity
Operation	70°C	0% RH
Storage	85°C	0% RH

Table 3-2 Low Temperature

	Temperature	Humidity
Operation	0°C	0% RH
Storage	-40°C	0% RH

Table 3-3 High Humidity

	Temperature	Humidity
Operation	40°C	90% RH
Storage	40°C	93% RH

Table 3-4 Temperature Cycling

	Temperature
Operation	0°C
Operation	70°C¹
Storage	-40°C
Storage	85°C

Notes:

1. The operation temperature is measured by the case temperature, in which can be decided via the S.M.A.R.T. Airflow is suggested and it will allow device to be operated at appropriate temperature for each component during heavy workloads environment.

3.1.2. Shock

Table 3-5 Shock

	Acceleration Force
Non-operational	1500G

3.1.3. Vibration

Table 3-6 Vibration

	Cond	ition
	Frequency/Displacement	Frequency/Acceleration
Non-operational	20Hz~80Hz/1.52mm	80Hz~2000Hz/20G

3.1.4. Drop

Table 3-7 Drop

		Height of Drop		Number of Drop
Non-operational		80cm free fall		6 face of each unit
3.1.5. Bending		Table 3-8 Bending
		Force		Action
Non-operational		≥ 20N		Hold 1min/5times
3.1.6. Torque		Table 3-9 Torque
		Force		Action
Non-operational		0.5N-m or ±2.5 deg		Hold 1min/5times
3.1.7. Electrostatic Discharge (ESD)		Table 3-10 ESD
Specification			+/- 4KV
EN 55024, CISPR 24 EN 61000-4-2 and IEC 61000-4-2	Device functions are affected, but EUT will be back to its normal or operational state automatically.

4. ELECTRICAL SPECIFICATIONS

4.1. Supply Voltage

Table 4-1 Supply Voltage

Parameter	Rating
Operating Voltage	Min = 3.14 V Max = 3.47 V
Rise Time (Max/Min)	10 ms / 0.1 ms
Fall Time (Max/Min)	1500 ms / 1 ms
Min. Off Time¹	1500 ms

NOTE:

1. Minimum time between power removed from SSD (Vcc < 100 mV) and power re-applied to the drive.

4.2. Power Consumption

Table 4-2 Power Consumption in mW

Capacity	Flash Configuration	CE#	Read (Max)	Write (Max)	Read (Avg.)	Write (Avg.)
128GB	DDP x 1	2	3200	2930	2940	2530
256GB	DDP x 2	4	4650	4560	4120	3400
512GB	QDP x 2	8	5260	4190	4090	3390
1024GB	QDP x 4	16	5350	6070	4050	3380
2048GB	ODP x 4	16	6320	6650	4440	3810

NOTES:

Based on APF1Mxxx-series under ambient temperature.

The average value of power consumption is achieved based on 100% conversion efficiency.

The measured power voltage is 3.3V.

The temperature of a storage device in PS1 should remain constant or should slightly decrease for all workloads so the actual power in PS1 should be lower than PS0.

The temperature of a storage device in PS2 should decrease sharply for all workloads so the actual power in PS2 should be lower than PS1.

5. INTERFACE

5.1. Pin Assignment and Descriptions

Table 5-1 defines the signal assignment of the internal NGFF connector for SSD usage, described in the PCI Express M.2 Specification version 1.0 of the PCI-SIG.

Table 5-1 Pin Assignment and Description of HG2283 M.2 2280

Pin No.	PCIe Pin	Description
1	GND	CONFIG_3 = GND
2	3.3V	3.3V source
3	GND	Ground
4	3.3V	3.3V source
5	PETn3	PCIe TX Differential signal defined by the PCI Express M.2 spec
6	N/C	No connect
7	PETp3	PCIe TX Differential signal defined by the PCI Express M.2 spec
8	N/C	No connect
9	GND	Ground
10	LED1#	Open drain, active low signal. These signals are used to allow the add-in card to provide status indicators via LED devices that will be provided by the system.
11	PERn3	PCIe RX Differential signal defined by the PCI Express M.2 spec
12	3.3V	3.3V source
13	PERp3	PCIe RX Differential signal defined by the PCI Express M.2 spec
14	3.3V	3.3V source
15	GND	Ground
16	3.3V	3.3V source
17	PETn2	PCIe TX Differential signal defined by the PCI Express M.2 spec
18	3.3V	3.3V source
19	PETp2	PCIe TX Differential signal defined by the PCI Express M.2 spec
20	N/C	No connect
21	GND	Ground
22	N/C	No connect
23	PERn2	PCIe RX Differential signal defined by the PCI Express M.2 spec
24	N/C	No connect
25	PERp2	PCIe RX Differential signal defined by the PCI Express M.2 spec
26	N/C	No connect
27	GND	Ground
28	N/C	No connect
29	PETn1	PCIe TX Differential signal defined by the PCI Express M.2 spec
30	N/C	No connect
31	PETp1	PCIe TX Differential signal defined by the PCI Express M.2 spec
32	GND	Ground
33	GND	Ground
34	N/C	No connect
35	PERn1	PCIe RX Differential signal defined by the PCI Express M.2 spec
36	N/C	No connect
37	PERp1	PCIe RX Differential signal defined by the PCI Express M.2 spec

Pin No.	PCIe Pin	Description
38 N/C		No connect
39 GND		Ground
40 SMB_CLK (I/O)(0/1.8V)		SMBus Clock; Open Drain with pull-up on platform
41	PETn0	PCIe TX Differential signal defined by the PCI Express M.2 spec
42	SMB_DATA (I/O)(0/1.8V)	SMBus Data; Open Drain with pull-up on platform.
43	PETp0	PCIe TX Differential signal defined by the PCI Express M.2 spec
44	ALERT#(O) (0/1.8V)	Alert notification to master; Open Drain with pull-up on platform; Active low.
45	GND	Ground
46	N/C	No connect
47	PERn0	PCIe RX Differential signal defined by the PCI Express M.2 spec
48	N/C	No connect
49	PERp0	PCIe RX Differential signal defined by the PCI Express M.2 spec
50	PERST#(I)(0/3.3V)	PE-Reset is a functional reset to the card as defined by the PCIe Mini CEM specification.
51	GND	Ground
52	CLKREQ#(I/O)(0/3.3V)	Clock Request is a reference clock request signal as defined by the PCIe Mini CEM specification; Also used by L1 PM Sub-states.
53	REFCLKn	PCIe Reference Clock signals (100 MHz) defined by the PCI Express M.2 spec.
54	PEWAKE#(I/O)(0/3.3V)	PCIe PME Wake. Open Drain with pull up on platform; Active Low.
55	REFCLKp	PCIe Reference Clock signals (100 MHz) defined by the PCI Express M.2 spec.
56	Reserved for MFG DATA	Manufacturing Data line. Used for SSD manufacturing only. Not used in normal operation. Pins should be left N/C in platform Socket.
57	GND	Ground
58	Reserved for MFG CLOCK	Manufacturing Clock line. Used for SSD manufacturing only. Not used in normal operation. Pins should be left N/C in platform Socket.
59	Module Key M	Module Key
60	Module Key M
61	Module Key M
62	Module Key M
63	Module Key M
64	Module Key M
65	Module Key M
66	Module Key M
67	N/C	No connect
68	SUSCLK(32KHz) (I)(0/3.3V)	32.768 kHz clock supply input that is provided by the platform chipset to reduce power and cost for the module.
69	NC	CONFIG_1 = No connect
70	3.3V	3.3V source
71	GND	Ground
72	3.3V	3.3V source
73	GND	Ground
74	3.3V	3.3V source
75	GND	CONFIG_2 = Ground

7. PHYSICAL DIMENSION

Form factor: M.2 2280 S2

Dimensions: 80.00mm (L) x 22.00mm (W) x 2.15mm (H)

View Direction	Diagram
Top
Bottom
View Direction	Diagram
Side

product-759-182

Figure 7-1 Product Mechanical Diagram and Dimensions

8. APPLICATION NOTES

8.1. Wafer Level Chip Scale Packaging (WLCSP) Handling Precautions

There are a lot of components assembled on a single SSD device. Please handle the drive with care especially when it has any WLCSP (Wafer Level Chip Scale Packaging) components such as PMIC, thermal sensor or load switch. WLCSP is one of the packaging technologies that is widely adopted for making smaller footprints, but any bumps or scratches may damage those ultrasmall parts so gentle handling is strongly recommended.

DO NOT DROP SSD

INSTALL SSD WITH CARE

TORE SSD IN A PROPER PACKAGE

8.2. M Key M.2 SSD Assembly Precautions

M Key M.2 SSD (Figure 1) is only compatible to M Key (Figure 2) socket. As shown in Use Case 2, misuse may cause severe damages to SSD including burn-out.

Figure 8-1 M Key M.2 Assembly Precautions

product-1007-439

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