Internal structure of NAND Flash

In 1965, after the bipolar tube was invented by W. Shockley, W. Brattain and J. Bardeen, Gordon Moore, the co-founder of Intel, discovered such a rule: when the price remains unchanged, the amount of energy that can be accommodated on an integrated circuit The number of transistors will double about every year, and the performance will also double. In fact, the number of transistors on an integrated circuit will double roughly every 18 months over the next few years. For example, in the 18 months between Pentium 1.3 and Pentium 4, the number of transistors per unit area increased from 28 million to 55 million.

Today, the operating frequency of the processor of a standard desktop PC is calculated in gigahertz, and the capacity information that the memory can store is calculated in terabytes (TB).This increase in the number of transistors per unit area is exemplified by memory, which also happens to be a key component in electronic systems.

Semiconductor memory can be divided into two main parts: RAM (Random Access Memories) and ROM (Read Only Memories): RAM will disappear after the power is turned off, while ROM will keep it. Another kind of memory, NVM (Non-Volatile Memories), is between the above two types. Its content can be modified, and the data will not be lost after a power failure. This is more flexible than pure ROM, because the content of ROM is written by the manufacturer and cannot be modified by the customer.

The history of Non-Volatile Memories began in the 1970s, and the first NVM was EPROM (Erasable Programmable Read Only Memory), since then until the 1990s, NVM has gradually become one of the most important members of the semiconductor family, and more attention has been paid to the development of new technologies to promote the progress of NVM more than the resulting economic benefits.

Since the 1990s, as semiconductor memory has entered digital terminal products such as mobile phones, handheld computers, and video cameras, this market has been in a state of rapid growth until today.

The most popular Flash memory storage method is based on a technology called Floating Gate (FG). You can refer to the following cross-sectional diagram. A MOS tube is composed of two overlapping gates: the first is completely surrounded by oxides ; while the second is connected to the outside. This single door is equivalent to forming an electronic isolation belt, which ensures that the electrons (data) in it can be retained for many years. The process of charging and discharging this isolated part is called program and erase. Due to the charging and discharging, the potential Vth inside the isolated part will be changed; this is the working principle of a typical MOS tube. When we apply a voltage to a memory cell, we can distinguish two cases: when the voltage we apply is higher than Vth, it is recognized as "1", otherwise it is recognized as "0".

NAND memory cell structure

Array

The storage units of the memory are organized in the form of a matrix, because this organization can effectively reduce the space occupied by the memory. I can tell the difference between NAND and NOR Flash by looking at the organization of the memory cells. We introduce NAND now, because NAND is the most widely used memory at present.

In the NAND architecture, memory cells are organized in series every 32 or 64 as shown in Figure 2.2. Two transistors for selection (the two external pins of this transistor are DSL/Mdl [connected to BL] or SSL/Msl [connected to SL]) are placed at both ends of each string of memory cells (32 or 64) to This ensures connection to the source line (via Msl) and bitline (via Mdl). Each NAND memory cell string has a bitline used to connect to other strings. Control gates are used to connect wordlines (WLs).

Logical pages are the part controlled by the storage unit controlled by the same wordline. The number of pages controlled by each wordline is related to the capacity of the storage unit. Based on the storage level of the storage unit, Flash memory can be divided into different categories: SLC (one storage unit 1bit), MLS (one storage unit 2bits), 8LC (one storage unit 3bits), 16LC (one storage unit 4bits).

If we consider the interleaving case of SLC, odd and even numbers form different pages respectively. An example is: an SLC wordline with a page size of 4KB (4096 * 8 = 32768 bits) has 65536 memory locations.

Of course, if it is MLC, there are 4 pages, and each memory cell series has one LSB (Least Significant Bit) and one MSB (Most Significant Bit). Hence there are:

- MSB and LSB pages of even bitlines

 - MSB and LSB pages of odd bitlines

All NAND memory cell strings of the same wordline are erased together when erasing, thus forming a block (blcok), if two blocks are shown in 2.2, the same bus is used, one The block is composed of WL0<63:0> and the other one is WL1<63:0>.

The memory cell structure of NAND Flash is a matrix. Additional circuits are required when reading, writing and erasing NAND. Since each die of NAND must be packaged, a suitable one is set in the design stage. It is important to size and build the surrounding electronics. For example, the hierarchical structure of each die of NAND Flash is like this.

Figure 2.3 shows an example of a hierarchy. The storage array can be set up as multiple planes (two planes in Figure 2.3), marked with wordlines in the horizontal direction and bitlines in the vertical direction.

The Row Decoder is located between the two planes. One of the tasks of the circuit is to properly bias the wordlines of the selected NAND strings to ensure normal operation. All bitlines must be connected to sense amplifiers (Sense Amp). Each sense amplifier can have one or more bitlines, which we will introduce in detail later in this section. The purpose of the sense amplifier is to convert the current in the memory cell to a digital quantity. In the peripheral area, there are some devices required to charge the memory cells, as well as voltage management devices, logic circuits, and other devices. PADs are used to communicate with external devices.